Changeset 400 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm


Ignore:
Timestamp:
Apr 20, 2012, 2:30:16 PM (13 years ago)
Author:
aitotat@…
google:author:
aitotat@gmail.com
Message:

Changes to XTIDE Universal BIOS:

  • Moved 8-bit device support to MODULE_8BIT_IDE.
  • JR-IDE/ISA support requires a lot less bytes.
  • AT builds now always use full operating mode.
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/XTIDE_Universal_BIOS/Src/Device/IDE/IdeIO.asm

    r376 r400  
    2323;--------------------------------------------------------------------
    2424; IdeIO_OutputALtoIdeControlBlockRegisterInDL
     25;   Parameters:
     26;       AL:     Byte to output
     27;       DL:     IDE Control Block Register
     28;       DS:DI:  Ptr to DPT (in RAMVARS segment)
     29;   Returns:
     30;       Nothing
     31;   Corrupts registers:
     32;       BX, DX
     33;--------------------------------------------------------------------
     34IdeIO_OutputALtoIdeControlBlockRegisterInDL:
     35%ifdef MODULE_8BIT_IDE
     36    mov     dh, [di+DPT_ATA.bDevice]
     37%ifdef MODULE_JRIDE
     38    test    dh, dh
     39    jnz     SHORT .OutputToIoMappedIde
     40
     41    add     dx, JRIDE_CONTROL_BLOCK_REGISTER_WINDOW_OFFSET
     42    jmp     SHORT OutputToJrIdeRegister
     43.OutputToIoMappedIde:
     44%endif
     45%endif
     46
     47    mov     bl, IDEVARS.wPortCtrl
     48    jmp     SHORT OutputALtoIdeRegisterInDLwithIdevarsOffsetToBasePortInBL
     49
     50
     51;--------------------------------------------------------------------
    2552; IdeIO_OutputALtoIdeRegisterInDL
    2653;   Parameters:
    2754;       AL:     Byte to output
    28 ;       DL:     IDE Control Block Register  (IdeIO_OutputALtoIdeControlBlockRegisterInDL)
    29 ;               IDE Register                (IdeIO_OutputALtoIdeRegisterInDL)
     55;       DL:     IDE Command Block Register
    3056;       DS:DI:  Ptr to DPT (in RAMVARS segment)
    3157;   Returns:
    … …  
    3561;--------------------------------------------------------------------
    3662ALIGN JUMP_ALIGN
    37 IdeIO_OutputALtoIdeControlBlockRegisterInDL:
    38     mov     bl, IDEVARS.wPortCtrl
    39     SKIP2B  f   ; cmp ax, <next instruction>
    40     ; Fall to IdeIO_OutputALtoIdeRegisterInDL
     63IdeIO_OutputALtoIdeRegisterInDL:
     64%ifdef MODULE_8BIT_IDE
     65    mov     dh, [di+DPT_ATA.bDevice]
     66%ifdef MODULE_JRIDE
     67    test    dh, dh
     68    jnz     SHORT OutputALtoIOmappedIdeRegisterInDL
    4169
    42 IdeIO_OutputALtoIdeRegisterInDL:
     70    add     dx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET
     71OutputToJrIdeRegister:
     72    mov     bx, dx
     73    mov     [cs:bx], al
     74    ret
     75ALIGN JUMP_ALIGN
     76OutputALtoIOmappedIdeRegisterInDL:
     77%endif
     78%endif
     79
    4380    mov     bl, IDEVARS.wPort
    44     call    GetPortToDXandTranslateA0andA3ifNecessary
     81OutputALtoIdeRegisterInDLwithIdevarsOffsetToBasePortInBL:
     82    call    GetIdePortToDX
    4583    out     dx, al
    4684    ret
    4785
     86
     87;--------------------------------------------------------------------
     88; IdeIO_InputStatusRegisterToAL
     89;   Parameters:
     90;       DS:DI:  Ptr to DPT (in RAMVARS segment)
     91;   Returns:
     92;       AL:     IDE Status Register contents
     93;   Corrupts registers:
     94;       BX, DX
     95;--------------------------------------------------------------------
     96ALIGN JUMP_ALIGN
     97IdeIO_InputStatusRegisterToAL:
     98    mov     dl, STATUS_REGISTER_in
     99    ; Fall to IdeIO_InputToALfromIdeRegisterInDL
    48100
    49101;--------------------------------------------------------------------
    … …  
    57109;       BX, DX
    58110;--------------------------------------------------------------------
    59 ALIGN JUMP_ALIGN
    60111IdeIO_InputToALfromIdeRegisterInDL:
     112%ifdef MODULE_8BIT_IDE
     113    mov     dh, [di+DPT_ATA.bDevice]
     114%ifdef MODULE_JRIDE
     115    test    dh, dh
     116    jnz     SHORT .InputToALfromIOmappedIdeRegisterInDL
     117
     118    add     dx, JRIDE_COMMAND_BLOCK_REGISTER_WINDOW_OFFSET
     119    mov     bx, dx
     120    mov     al, [cs:bx]
     121    ret
     122.InputToALfromIOmappedIdeRegisterInDL:
     123%endif
     124%endif
    61125    mov     bl, IDEVARS.wPort
    62     call    GetPortToDXandTranslateA0andA3ifNecessary
     126    call    GetIdePortToDX
    63127    in      al, dx
    64128    ret
    … …  
    66130
    67131;--------------------------------------------------------------------
    68 ; GetPortToDXandTranslateA0andA3ifNecessary
     132; GetIdePortToDX
    69133;   Parameters:
    70134;       BL:     Offset to port in IDEVARS (IDEVARS.wPort or IDEVARS.wPortCtrl)
     135;       DH:     Device Type (IDEVARS.bDevice)
    71136;       DL:     IDE Register
    72137;       DS:DI:  Ptr to DPT (in RAMVARS segment)
    … …  
    77142;--------------------------------------------------------------------
    78143ALIGN JUMP_ALIGN
    79 GetPortToDXandTranslateA0andA3ifNecessary:
     144GetIdePortToDX:
     145%ifdef MODULE_8BIT_IDE
     146    ; Point CS:BX to IDEVARS
    80147    xor     bh, bh
    81     add     bl, [di+DPT.bIdevarsOffset]     ; CS:BX now points port address
    82     xor     dh, dh                          ; DX now has IDE register offset
    83     add     dx, [cs:bx]
    84     test    BYTE [di+DPT.bFlagsHigh], FLGH_DPT_REVERSED_A0_AND_A3
    85     jz      SHORT .ReturnPortInDX
     148    add     bl, [di+DPT.bIdevarsOffset]         ; CS:BX now points port address
     149
     150    ; Load port address and check if A0 and A3 address lines need to be reversed
     151    cmp     dh, DEVICE_8BIT_XTIDE_REV1
     152    mov     dh, bh                              ; DX now has IDE register offset
     153    jae     SHORT .ReturnUntranslatedPortInDX   ; No need to swap address lines
    86154
    87155    ; Exchange address lines A0 and A3 from DL
     156    add     dx, [cs:bx]                         ; DX now has port address
    88157    mov     bl, dl
    89158    mov     bh, MASK_A3_AND_A0_ADDRESS_LINES
    90     and     bh, bl                          ; BH = 0, 1, 8 or 9, we can ignore 0 and 9
    91     jz      SHORT .ReturnPortInDX           ; Jump out since DH is 0
     159    and     bh, bl                              ; BH = 0, 1, 8 or 9, we can ignore 0 and 9
     160    jz      SHORT .ReturnTranslatedPortInDX     ; Jump out since DH is 0
    92161    xor     bh, MASK_A3_AND_A0_ADDRESS_LINES
    93     jz      SHORT .ReturnPortInDX           ; Jump out since DH was 9
     162    jz      SHORT .ReturnTranslatedPortInDX     ; Jump out since DH was 9
    94163    and     dl, ~MASK_A3_AND_A0_ADDRESS_LINES
    95     or      dl, bh                          ; Address lines now reversed
    96 .ReturnPortInDX:
     164    or      dl, bh                              ; Address lines now reversed
     165.ReturnTranslatedPortInDX:
    97166    ret
     167
     168.ReturnUntranslatedPortInDX:
     169    add     dx, [cs:bx]
     170    ret
     171
     172%else   ; Only standard IDE devices
     173    xor     bh, bh
     174    xor     dh, dh
     175    add     bl, [di+DPT.bIdevarsOffset]     ; CS:BX now points port address
     176    add     dx, [cs:bx]                     ; DX now has port address
     177    ret
     178%endif
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