1 | ; Project name : XTIDE Universal BIOS |
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2 | ; Description : IDE Register I/O functions. |
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3 | |
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4 | ; |
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5 | ; XTIDE Universal BIOS and Associated Tools |
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6 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2012 by XTIDE Universal BIOS Team. |
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7 | ; |
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8 | ; This program is free software; you can redistribute it and/or modify |
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9 | ; it under the terms of the GNU General Public License as published by |
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10 | ; the Free Software Foundation; either version 2 of the License, or |
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11 | ; (at your option) any later version. |
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12 | ; |
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13 | ; This program is distributed in the hope that it will be useful, |
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14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | ; GNU General Public License for more details. |
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17 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html |
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18 | ; |
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19 | |
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20 | ; Section containing code |
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21 | SECTION .text |
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22 | |
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23 | ;-------------------------------------------------------------------- |
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24 | ; IdeIO_OutputALtoIdeControlBlockRegisterInDL |
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25 | ; IdeIO_OutputALtoIdeRegisterInDL |
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26 | ; Parameters: |
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27 | ; AL: Byte to output |
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28 | ; DL: IDE Control Block Register (IdeIO_OutputALtoIdeControlBlockRegisterInDL) |
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29 | ; IDE Register (IdeIO_OutputALtoIdeRegisterInDL) |
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30 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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31 | ; Returns: |
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32 | ; Nothing |
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33 | ; Corrupts registers: |
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34 | ; BX, DX |
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35 | ;-------------------------------------------------------------------- |
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36 | ALIGN JUMP_ALIGN |
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37 | IdeIO_OutputALtoIdeControlBlockRegisterInDL: |
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38 | mov bl, IDEVARS.wPortCtrl |
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39 | SKIP2B f ; cmp ax, <next instruction> |
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40 | ; Fall to IdeIO_OutputALtoIdeRegisterInDL |
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41 | |
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42 | IdeIO_OutputALtoIdeRegisterInDL: |
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43 | mov bl, IDEVARS.wPort |
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44 | call GetPortToDXandTranslateA0andA3ifNecessary |
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45 | out dx, al |
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46 | ret |
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47 | |
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48 | |
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49 | ;-------------------------------------------------------------------- |
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50 | ; IdeIO_InputToALfromIdeRegisterInDL |
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51 | ; Parameters: |
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52 | ; DL: IDE Register |
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53 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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54 | ; Returns: |
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55 | ; AL: Inputted byte |
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56 | ; Corrupts registers: |
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57 | ; BX, DX |
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58 | ;-------------------------------------------------------------------- |
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59 | ALIGN JUMP_ALIGN |
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60 | IdeIO_InputToALfromIdeRegisterInDL: |
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61 | mov bl, IDEVARS.wPort |
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62 | call GetPortToDXandTranslateA0andA3ifNecessary |
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63 | in al, dx |
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64 | ret |
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65 | |
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66 | |
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67 | ;-------------------------------------------------------------------- |
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68 | ; GetPortToDXandTranslateA0andA3ifNecessary |
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69 | ; Parameters: |
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70 | ; BL: Offset to port in IDEVARS (IDEVARS.wPort or IDEVARS.wPortCtrl) |
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71 | ; DL: IDE Register |
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72 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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73 | ; Returns: |
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74 | ; DX: Source/Destination Port |
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75 | ; Corrupts registers: |
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76 | ; BX |
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77 | ;-------------------------------------------------------------------- |
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78 | ALIGN JUMP_ALIGN |
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79 | GetPortToDXandTranslateA0andA3ifNecessary: |
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80 | xor bh, bh |
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81 | add bl, [di+DPT.bIdevarsOffset] ; CS:BX now points port address |
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82 | xor dh, dh ; DX now has IDE register offset |
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83 | add dx, [cs:bx] |
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84 | test BYTE [di+DPT.bFlagsHigh], FLGH_DPT_REVERSED_A0_AND_A3 |
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85 | jz SHORT .ReturnPortInDX |
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86 | |
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87 | ; Exchange address lines A0 and A3 from DL |
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88 | mov bl, dl |
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89 | mov bh, MASK_A3_AND_A0_ADDRESS_LINES |
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90 | and bh, bl ; BH = 0, 1, 8 or 9, we can ignore 0 and 9 |
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91 | jz SHORT .ReturnPortInDX ; Jump out since DH is 0 |
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92 | xor bh, MASK_A3_AND_A0_ADDRESS_LINES |
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93 | jz SHORT .ReturnPortInDX ; Jump out since DH was 9 |
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94 | and dl, ~MASK_A3_AND_A0_ADDRESS_LINES |
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95 | or dl, bh ; Address lines now reversed |
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96 | .ReturnPortInDX: |
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97 | ret |
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