Changeset 622 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS/Inc/Controllers/PDC20x30.inc


Ignore:
Timestamp:
Dec 16, 2021, 5:46:51 PM (2 years ago)
Author:
aitotat
Message:
  • Supported VLB controllers are now forced to 32-bit mode on 386 builds only. AT builds use 16-bit transfers unless configured to 32-bit from xtidecfg
  • Partially fixed support for PDC 20230C VLB IDE controller. PIO-1 drives stay at PIO-0 but PIO-2, 3 and 4 drives are set to maximum speed that PDC2030C supports
  • Large 386 build is now 12k instead of 10k (did not fit to 10k because of the fixes)
File:
1 edited

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  • trunk/XTIDE_Universal_BIOS/Inc/Controllers/PDC20x30.inc

    r589 r622  
    2222%define PDC20x30_INC
    2323
     24;
    2425
    25 ; SECTOR_COUNT_REGISTER in programming mode
    26 FLG_PDCSCR_UNKNOWN_BIT7     EQU     (1<<7)  ; Set to 1 for speed setting 7 of device 0 or 1
    27 FLG_PDCSCR_ID3              EQU     (1<<6)  ; VLB bus speed: 0 > 33 MHz, 1 <= 33 MHz
    28 POS_PDCSCR_DEV0SPEED        EQU     3
    29 MASK_PDCSCR_DEV0SPEED       EQU     (7<<POS_PDCSCR_DEV0SPEED)   ; 0 to 7
    30 MASK_PDCSCR_DEV1SPEED       EQU     (7<<0)                      ; 0 to 7
     26; SECTOR_COUNT_REGISTER (1F2) in programming mode
     27FLG_PDCSCR_BOTHMAX          EQU     (1<<6)  ; Master and Slave at maximum speed
     28
     29; SECTOR_NUMBER_REGISTER (1F3) in programming mode
     30FLG_PDCSNR_UNKNOWN_BIT7     EQU     (1<<7)  ; Set to 1 for speed setting 7 of device 0 or 1
     31FLG_PDCSNR_ID3              EQU     (1<<6)  ; VLB bus speed: 0 > 33 MHz, 1 <= 33 MHz
     32POS_PDCSNR_DEV0SPEED        EQU     3
     33MASK_PDCSNR_DEV0SPEED       EQU     (7<<POS_PDCSNR_DEV0SPEED)   ; 0 to 7
     34MASK_PDCSNR_DEV1SPEED       EQU     (7<<0)                      ; 0 to 7
     35
     36; Disassembly of VG4.BIN: (might have errors)
     37; FLG_PDCSNR_UNKNOWN_BIT7 will be set if no dev1, no matter what speed
     38; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev1 found but no master
     39; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev0 and dev1 speeds are both 7 !
     40; FLG_PDCSNR_UNKNOWN_BIT7 will be cleared if dev 1 is 7 !
     41; If dev 1 is 6 or less and dev 0 is 7, then dev0-- and set FLG_PDCSCR_UNKNOWN_BIT7
     42;
     43
    3144
    3245
    … …  
    3649FLG_PDCLCR_DEV1SPEED_BIT4   EQU     (1<<6)  ; Same as above but for device 1
    3750FLG_PDCLCR_DEV0IORDY        EQU     (1<<5)  ; Not sure about this
    38 FLG_PDCLCR_DEV1IORDY        EQU     (1<<4)  ; Same as above but for device 15
     51FLG_PDCLCR_DEV1IORDY        EQU     (1<<4)  ; Same as above but for device 1
    3952FLG_PDCLCR_ENABLE_EXTRA_REGISTERS   EQU (1<<3)
    4053
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