Changeset 536 in xtideuniversalbios for trunk/XTIDE_Universal_BIOS_Configurator_v2/Src/Strings.asm

Timestamp:

Apr 10, 2013, 6:27:15 PM (12 years ago)

Author:

krille_n_@…

google:author:

krille_n_@hotmail.com

Message:

Changes:

• Added support for the Silicon Valley Computer ADP50L controller (and possibly other IDE controllers from SVC using memory mapped I/O). Please note that this has not been tested in any way since I don't have any of these cards myself (make backups before trying this on drives with important data). Also, *if* it works, make sure it works reliably (stress test the disk system). Some things you should know: 1) Autodetection for this controller has not been added to XTIDECFG, you need to manually select the "SVC ADP50L" controller (and possibly change the BIOS segment address if not using the default of C800h). 2) The memory mapped I/O window is inside the ROM address space of the controller. The XTIDE Universal BIOS currently do not support this so that means you need to use another ROM (for example, an XTIDE or XTCF card or the BOOT ROM of a NIC). This presents another problem, the original ADP50L BIOS needs to be disabled somehow to avoid conflicts. Either pull the ROM chip or disable the BIOS by removing jumper J3. Note, I have no idea if any of this will actually work. It's basically a shot in the dark.

File:

• trunk/XTIDE_Universal_BIOS_Configurator_v2/Src/Strings.asm (modified) (4 diffs)

trunk/XTIDE_Universal_BIOS_Configurator_v2/Src/Strings.asm

@@ -228 +228 @@
 g_szNfoIdeSlave:            db  "Settings for Slave Drive.",NULL
 g_szNfoIdeDevice:           db  "Select controller device type.",NULL
-g_szNfoIdeCmdPort:          db  "IDE Controller Command Block (base port) address or segment address for JR-IDE/ISA.",NULL
+g_szNfoIdeCmdPort:          db  "IDE Controller Command Block (base port) address or segment address for JR-IDE/ISA and SVC ADP50L.",NULL
 g_szNfoIdeCtrlPort:         db  "IDE Controller Control Block address. Usually Cmd Block + 8 for XTIDE, and Cmd Block + 200h for ATA.",NULL
 g_szNfoIdeEnIRQ:            db  "Interrupt or polling mode.",NULL
@@ -241 +241 @@
                             db  " By default the primary IDE controller uses port 1F0h and secondary controller uses port 170h."
                             db  " XTIDE card uses port 300h by default."
-                            db  " JR-IDE/ISA do not use ports but you need to set ROM space segment address for JR-IDE/ISA.",NULL
+                            db  " JR-IDE/ISA and SVC ADP50L do not use ports but needs the ROM segment address set here instead.",NULL
 
 g_szHelpIdeCtrlPort:        db  "IDE controller Control Block address is normally Command Block address + 200h."
@@ -282 +282 @@
                             db  "XT-CF v2 in memory mode",LF
                             db  "JR-IDE/ISA",LF
+                            db  "SVC ADP50L",LF
                             db  "Serial port virtual device",NULL
 
@@ -293 +294 @@
 g_szValueCfgDeviceMemXTCF:  db  "XTCF MEM",NULL
 g_szValueCfgDeviceJrIdeIsa: db  "JR-ISA",NULL
+g_szValueCfgDeviceADP50L:   db  "ADP50L",NULL
 g_szValueCfgDeviceSerial:   db  "Serial",NULL