1 | ; Project name : XTIDE Universal BIOS |
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2 | ; Description : Functions for initializing QDI Vision |
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3 | ; QD6500 and QD6580 VLB IDE Controllers. |
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4 | |
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5 | ; |
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6 | ; XTIDE Universal BIOS and Associated Tools |
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7 | ; Copyright (C) 2009-2010 by Tomi Tilli, 2011-2013 by XTIDE Universal BIOS Team. |
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8 | ; |
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9 | ; This program is free software; you can redistribute it and/or modify |
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10 | ; it under the terms of the GNU General Public License as published by |
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11 | ; the Free Software Foundation; either version 2 of the License, or |
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12 | ; (at your option) any later version. |
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13 | ; |
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14 | ; This program is distributed in the hope that it will be useful, |
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15 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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17 | ; GNU General Public License for more details. |
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18 | ; Visit http://www.gnu.org/licenses/old-licenses/gpl-2.0.html |
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19 | ; |
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20 | |
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21 | ; Section containing code |
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22 | SECTION .text |
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23 | |
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24 | ;-------------------------------------------------------------------- |
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25 | ; Vision_DetectAndReturnIDinAXandPortInDXifControllerPresent |
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26 | ; Parameters: |
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27 | ; Nothing |
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28 | ; Returns: |
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29 | ; AX: ID WORD specific for QDI Vision Controllers |
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30 | ; (AL = QD65xx Config Register contents) |
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31 | ; (AH = QDI Vision Controller ID) |
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32 | ; DX: Controller port (not IDE port) |
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33 | ; ZF: Set if controller found |
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34 | ; Cleared if supported controller not found (AX,DX = undefined) |
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35 | ; Corrupts registers: |
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36 | ; Nothing |
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37 | ;-------------------------------------------------------------------- |
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38 | Vision_DetectAndReturnIDinAXandPortInDXifControllerPresent: |
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39 | ; Check QD65xx base port |
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40 | mov dx, QD65XX_BASE_PORT |
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41 | in al, QD65XX_BASE_PORT + QD65XX_CONFIG_REGISTER_in |
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42 | |
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43 | call IsConfigRegisterWithIDinAL |
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44 | je SHORT VisionControllerDetected.Return |
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45 | |
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46 | ; Check QD65xx alternative base port |
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47 | mov dl, QD65XX_ALTERNATIVE_BASE_PORT |
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48 | in al, QD65XX_ALTERNATIVE_BASE_PORT + QD65XX_CONFIG_REGISTER_in |
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49 | ; Fall to IsConfigRegisterWithIDinAL |
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50 | |
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51 | ;-------------------------------------------------------------------- |
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52 | ; IsConfigRegisterWithIDinAL |
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53 | ; Parameters: |
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54 | ; AL: Possible QD65xx Config Register contents |
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55 | ; Returns: |
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56 | ; AH QDI Vision Controller ID or undefined |
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57 | ; ZF: Set if controller found |
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58 | ; Cleared if supported controller not found (AH = undefined) |
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59 | ; Corrupts registers: |
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60 | ; Nothing |
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61 | ;-------------------------------------------------------------------- |
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62 | IsConfigRegisterWithIDinAL: |
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63 | mov ah, al |
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64 | and al, MASK_QDCONFIG_CONTROLLER_ID |
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65 | cmp al, ID_QD6500 |
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66 | je SHORT VisionControllerDetected |
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67 | cmp al, ID_QD6580 |
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68 | je SHORT VisionControllerDetected |
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69 | cmp al, ID_QD6580_ALTERNATE |
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70 | VisionControllerDetected: |
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71 | xchg ah, al |
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72 | .Return: |
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73 | ret |
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74 | |
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75 | |
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76 | ;-------------------------------------------------------------------- |
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77 | ; Vision_DoesIdePortInBXbelongToControllerWithIDinAX |
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78 | ; Parameters: |
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79 | ; AL: QD65xx Config Register contents |
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80 | ; AH: QDI Vision Controller ID |
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81 | ; BX: IDE Base port to check |
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82 | ; DX: Vision Controller port |
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83 | ; Returns: |
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84 | ; ZF: Set if port belongs to controller |
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85 | ; Cleared if port belongs to another controller |
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86 | ; Corrupts registers: |
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87 | ; Nothing |
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88 | ;-------------------------------------------------------------------- |
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89 | Vision_DoesIdePortInBXbelongToControllerWithIDinAX: |
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90 | cmp ah, ID_QD6500 |
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91 | je SHORT .DoesIdePortInDXbelongToQD6500 |
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92 | |
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93 | ; QD6580 always have Primary IDE at 1F0h |
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94 | ; Secondary IDE at 170h can be enabled or disabled |
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95 | cmp bx, DEVICE_ATA_PRIMARY_PORT |
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96 | je SHORT .ReturnResultInZF |
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97 | |
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98 | ; Check if Secondary IDE channel is enabled |
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99 | push ax |
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100 | push dx |
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101 | add dx, BYTE QD6580_CONTROL_REGISTER |
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102 | in al, dx |
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103 | test al, FLG_QDCONTROL_SECONDARY_DISABLED_in |
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104 | pop dx |
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105 | pop ax |
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106 | jz SHORT .CompareBXtoSecondaryIDE |
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107 | ret |
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108 | |
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109 | ; QD6500 has only one IDE channel that can be at 1F0h or 170h |
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110 | .DoesIdePortInDXbelongToQD6500: |
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111 | test al, FLG_QDCONFIG_PRIMARY_IDE |
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112 | jz SHORT .CompareBXtoSecondaryIDE |
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113 | cmp bx, DEVICE_ATA_PRIMARY_PORT |
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114 | ret |
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115 | |
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116 | .CompareBXtoSecondaryIDE: |
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117 | cmp bx, DEVICE_ATA_SECONDARY_PORT |
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118 | .ReturnResultInZF: |
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119 | ret |
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120 | |
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121 | |
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122 | ;-------------------------------------------------------------------- |
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123 | ; Vision_GetMaxPioModeToALandMinCycleTimeToBX |
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124 | ; Parameters: |
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125 | ; AL: QD65xx Config Register contents |
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126 | ; AH: QDI Vision Controller ID |
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127 | ; Returns: |
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128 | ; AL: Max supported PIO mode (only if ZF set) |
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129 | ; AH: ~FLGH_DPT_IORDY if IORDY not supported, -1 otherwise (only if ZF set) |
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130 | ; BX: Min PIO Cycle Time (only if ZF set) |
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131 | ; ZF: Set if PIO limit necessary |
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132 | ; Cleared if no need to limit timings |
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133 | ; Corrupts registers: |
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134 | ; Nothing |
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135 | ;-------------------------------------------------------------------- |
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136 | Vision_GetMaxPioModeToALandMinCycleTimeToBX: |
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137 | cmp ah, ID_QD6500 |
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138 | jne SHORT .NoNeedToLimitForQD6580 |
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139 | mov ax, (~FLGH_DPT_IORDY & 0FFh) << 8 | 2 ; Limit to PIO 2 because QD6500 does not support IORDY |
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140 | mov bx, PIO_2_MIN_CYCLE_TIME_NS |
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141 | .NoNeedToLimitForQD6580: |
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142 | ret |
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143 | |
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144 | |
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145 | ;-------------------------------------------------------------------- |
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146 | ; Vision_InitializeWithIDinAH |
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147 | ; Parameters: |
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148 | ; AH: QDI Vision Controller ID |
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149 | ; DS:DI: Ptr to DPT for Single or Slave Drive |
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150 | ; SI: Offset to Master DPT if Slave Drive present |
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151 | ; Zero if Slave Drive not present |
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152 | ; Returns: |
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153 | ; CF: Cleared if success |
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154 | ; Set if error |
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155 | ; Corrupts registers: |
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156 | ; AX, BX, CX, DX, BP |
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157 | ;-------------------------------------------------------------------- |
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158 | Vision_InitializeWithIDinAH: |
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159 | ; QD6580 has a Control Register that needs to be programmed |
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160 | cmp ah, ID_QD6500 |
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161 | mov dx, [di+DPT_ADVANCED_ATA.wControllerBasePort] |
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162 | mov bp, QD6500_MAX_ACTIVE_TIME_CLOCKS | (QD6500_MIN_ACTIVE_TIME_CLOCKS << 8) ; Assume QD6500 |
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163 | je SHORT .CalculateTimingsForQD65xx |
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164 | mov bp, QD6580_MAX_ACTIVE_TIME_CLOCKS | (QD6580_MIN_ACTIVE_TIME_CLOCKS << 8) ; It's a QD6580 |
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165 | |
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166 | ; Program QD6580 Control Register (not available on QD6500) to |
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167 | ; Enable or Disable Read-Ahead and Post-Write Buffer to match |
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168 | ; jumper setting on the multi I/O card. |
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169 | add dx, BYTE QD6580_CONTROL_REGISTER |
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170 | in al, dx ; Read to get ATAPI jumper status |
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171 | test al, FLG_QDCONTROL_HDONLY_in |
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172 | mov al, MASK_QDCONTROL_FLAGS_TO_SET |
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173 | eCMOVNZ al, FLG_QDCONTROL_NONATAPI | MASK_QDCONTROL_FLAGS_TO_SET ; Enable Read-Ahead and Post-Write Buffers |
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174 | out dx, al |
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175 | dec dx ; Secondary Channel IDE Timing Register |
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176 | |
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177 | ; Now we need to determine is the drive connected to the Primary or Secondary channel. |
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178 | ; QD6500 has only one channel that can be Primary at 1F0h or Secondary at 170h. |
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179 | ; QD6580 always has Primary channel at 1F0h. Secondary channel at 170h can be Enabled or Disabled. |
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180 | cmp BYTE [di+DPT.wBasePort], DEVICE_ATA_SECONDARY_PORT & 0FFh |
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181 | je SHORT .CalculateTimingsForQD65xx ; Secondary Channel so no need to modify DX |
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182 | dec dx |
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183 | dec dx ; Primary Channel IDE Timing Register |
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184 | |
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185 | ; We need the PIO Cycle Time in CX to calculate Active and Recovery Times. |
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186 | .CalculateTimingsForQD65xx: |
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187 | call AdvAtaInit_SelectSlowestCommonPioTimingsToBXandCXfromDSSIandDSDI |
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188 | |
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189 | ; Calculate Active Time value for QD65xx IDE Timing Register |
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190 | call AtaID_GetActiveTimeToAXfromPioModeInBX |
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191 | call ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue |
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192 | xchg bp, ax |
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193 | |
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194 | ; Calculate Recovery Time value for QD65xx IDE Timing Register |
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195 | xchg ax, cx |
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196 | eMOVZX cx, BYTE [cs:bx+.rgbToSubtractFromCycleTimeBasedOnPIOmode] |
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197 | sub ax, cx |
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198 | mov bx, bp ; Active Time value now in BL |
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199 | mov bp, QD65xx_MAX_RECOVERY_TIME_CLOCKS | (QD65xx_MIN_RECOVERY_TIME_CLOCKS << 8) |
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200 | call ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue |
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201 | |
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202 | ; Merge the values to a single byte to output |
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203 | eSHL_IM al, POSITION_QD65XXIDE_RECOVERY_TIME |
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204 | or al, bl |
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205 | out dx, al |
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206 | ret ; Return with CF cleared |
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207 | |
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208 | .rgbToSubtractFromCycleTimeBasedOnPIOmode: |
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209 | ; For PIO 0 to 2 this method (t0 - (t1+t8+t9)) seems to give closest (little less) values to the fixed preset |
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210 | ; values used by QDI6580 DOS driver v3.7 |
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211 | db (PIO_0_MIN_ADDRESS_VALID_NS + PIO_0_MAX_ADDR_VALID_TO_IOCS16_RELEASED + PIO_0_DIORW_TO_ADDR_VALID_HOLD) |
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212 | db (PIO_1_MIN_ADDRESS_VALID_NS + PIO_1_MAX_ADDR_VALID_TO_IOCS16_RELEASED + PIO_1_DIORW_TO_ADDR_VALID_HOLD) |
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213 | db (PIO_2_MIN_ADDRESS_VALID_NS + PIO_2_MAX_ADDR_VALID_TO_IOCS16_RELEASED + PIO_2_DIORW_TO_ADDR_VALID_HOLD) |
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214 | db 102 ; QDI6580 DOS driver v3.7 uses fixed values for PIO 3... |
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215 | db 61 ; ...and PIO 4. No idea where these values come from. |
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216 | db (PIO_5_MIN_CYCLE_TIME_NS / 2) ; PIO 5 and 6 were not available when QD6850 was released. Use values... |
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217 | db (PIO_6_MIN_CYCLE_TIME_NS / 2) ; ...that resembles those used for PIO 4 |
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218 | |
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219 | |
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220 | ;-------------------------------------------------------------------- |
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221 | ; ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue |
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222 | ; Parameters: |
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223 | ; AX: Nanosecs to convert |
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224 | ; BP: Low Byte: Maximum allowed ticks |
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225 | ; High Byte: Minimum allowed ticks |
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226 | ; DS:DI: Ptr to DPT for Single or Slave Drive |
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227 | ; Returns: |
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228 | ; AL: Timing value for QD65xx register |
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229 | ; Corrupts registers: |
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230 | ; Nothing |
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231 | ;-------------------------------------------------------------------- |
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232 | ConvertNanosecsFromAXwithLimitsInBPtoRegisterValue: |
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233 | push cx |
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234 | |
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235 | ; Get VLB Cycle Time in nanosecs |
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236 | mov cl, VLB_33MHZ_CYCLE_TIME ; Assume 33 MHz or slower VLB bus (30 ns) |
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237 | test BYTE [di+DPT_ADVANCED_ATA.wControllerID], FLG_QDCONFIG_ID3 |
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238 | eCMOVZ cl, VLB_40MHZ_CYCLE_TIME ; (25 ns) |
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239 | |
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240 | ; Convert value in AX to VLB ticks |
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241 | div cl ; AL = VLB ticks |
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242 | inc ax ; Round up |
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243 | |
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244 | ; Limit value to QD65xx limits |
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245 | mov cx, bp |
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246 | MAX_U al, ch ; Make sure not below minimum |
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247 | MIN_U al, cl ; Make sure not above maximum |
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248 | |
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249 | ; Not done yet, we need to invert the ticks since 0 is the slowest |
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250 | ; value on the timing register |
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251 | sub cl, al |
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252 | xchg ax, cx ; Return in AL |
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253 | |
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254 | pop cx |
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255 | ret |
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