| 1 | ; Project name : XTIDE Universal BIOS |
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| 2 | ; Description : IDE Register I/O functions. |
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| 3 | |
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| 4 | ; Section containing code |
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| 5 | SECTION .text |
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| 6 | |
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| 7 | ;-------------------------------------------------------------------- |
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| 8 | ; IdeIO_OutputALtoIdeControlBlockRegisterInDL |
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| 9 | ; IdeIO_OutputALtoIdeRegisterInDL |
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| 10 | ; Parameters: |
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| 11 | ; AL: Byte to output |
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| 12 | ; DL: IDE Control Block Register (IdeIO_OutputALtoIdeControlBlockRegisterInDL) |
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| 13 | ; IDE Register (IdeIO_OutputALtoIdeRegisterInDL) |
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| 14 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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| 15 | ; Returns: |
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| 16 | ; Nothing |
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| 17 | ; Corrupts registers: |
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| 18 | ; BX, DX |
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| 19 | ;-------------------------------------------------------------------- |
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| 20 | ALIGN JUMP_ALIGN |
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| 21 | IdeIO_OutputALtoIdeControlBlockRegisterInDL: |
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| 22 | mov bl, IDEVARS.wPortCtrl |
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| 23 | SKIP2B f ; cmp ax, <next instruction> |
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| 24 | ; Fall to IdeIO_OutputALtoIdeRegisterInDL |
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| 25 | |
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| 26 | IdeIO_OutputALtoIdeRegisterInDL: |
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| 27 | mov bl, IDEVARS.wPort |
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| 28 | call GetPortToDXandTranslateA0andA3ifNecessary |
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| 29 | out dx, al |
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| 30 | ret |
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| 31 | |
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| 32 | |
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| 33 | ;-------------------------------------------------------------------- |
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| 34 | ; IdeIO_InputToALfromIdeRegisterInDL |
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| 35 | ; Parameters: |
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| 36 | ; DL: IDE Register |
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| 37 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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| 38 | ; Returns: |
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| 39 | ; AL: Inputted byte |
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| 40 | ; Corrupts registers: |
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| 41 | ; BX, DX |
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| 42 | ;-------------------------------------------------------------------- |
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| 43 | ALIGN JUMP_ALIGN |
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| 44 | IdeIO_InputToALfromIdeRegisterInDL: |
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| 45 | mov bl, IDEVARS.wPort |
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| 46 | call GetPortToDXandTranslateA0andA3ifNecessary |
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| 47 | in al, dx |
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| 48 | ret |
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| 49 | |
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| 50 | |
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| 51 | ;-------------------------------------------------------------------- |
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| 52 | ; GetPortToDXandTranslateA0andA3ifNecessary |
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| 53 | ; Parameters: |
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| 54 | ; BL: Offset to port in IDEVARS (IDEVARS.wPort or IDEVARS.wPortCtrl) |
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| 55 | ; DL: IDE Register |
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| 56 | ; DS:DI: Ptr to DPT (in RAMVARS segment) |
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| 57 | ; Returns: |
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| 58 | ; DX: Source/Destination Port |
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| 59 | ; Corrupts registers: |
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| 60 | ; BX |
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| 61 | ;-------------------------------------------------------------------- |
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| 62 | ALIGN JUMP_ALIGN |
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| 63 | GetPortToDXandTranslateA0andA3ifNecessary: |
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| 64 | xor bh, bh |
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| 65 | add bl, [di+DPT.bIdevarsOffset] ; CS:BX now points port address |
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| 66 | xor dh, dh ; DX now has IDE register offset |
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| 67 | add dx, [cs:bx] |
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| 68 | test BYTE [di+DPT.bFlagsHigh], FLGH_DPT_REVERSED_A0_AND_A3 |
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| 69 | jz SHORT .ReturnPortInDX |
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| 70 | |
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| 71 | ; Exchange address lines A0 and A3 from DL |
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| 72 | mov bl, dl |
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| 73 | mov bh, MASK_A3_AND_A0_ADDRESS_LINES |
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| 74 | and bh, bl ; BH = 0, 1, 8 or 9, we can ignore 0 and 9 |
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| 75 | jz SHORT .ReturnPortInDX ; Jump out since DH is 0 |
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| 76 | xor bh, MASK_A3_AND_A0_ADDRESS_LINES |
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| 77 | jz SHORT .ReturnPortInDX ; Jump out since DH was 9 |
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| 78 | and dl, ~MASK_A3_AND_A0_ADDRESS_LINES |
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| 79 | or dl, bh ; Address lines now reversed |
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| 80 | .ReturnPortInDX: |
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| 81 | ret |
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