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Last change
on this file since 567 was 567, checked in by krille_n_@…, 11 years ago |
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Changes:
- Renamed MODULE_FEATURE_SETS to MODULE_POWER_MANAGEMENT.
- Renamed MODULE_VERY_LATE_INITIALIZATION to MODULE_VERY_LATE_INIT and removed it from the official builds.
- Removed the code that skips detection of slave drives on XT-CF controllers since slave drives can be used with Lo-tech ISA CompactFlash boards.
- Added autodetection of the SVC ADP50L controller to XTIDECFG.
- The autodetection of XT-CF controllers now requires MODULE_8BIT_IDE_ADVANCED in the loaded BIOS.
- Fixed a bug in XTIDECFG from r502 where the "Base (cmd block) address" menu option would be displayed when a serial device was selected as the IDE controller.
- XTIDECFG would display the "Enable interrupt" menu option for the XTIDE r1 but not for the XTIDE r2. It's now displayed for both controller types.
- Disabled the "Internal Write Cache" menu option in the Master/Slave Drive menus for serial device type drives.
- Optimizations and other fixes.
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File size:
1.7 KB
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| 1 | ; Project name : Assembly Library
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| 2 | ; Description : Delay macros.
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| 3 | %ifndef DELAY_INC
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| 4 | %define DELAY_INC
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| 5 |
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| 6 | ;--------------------------------------------------------------------
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| 7 | ; Clears prefetch queue by jumping to next instruction.
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| 8 | ; This delays much more than nop instruction of fast systems.
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| 9 | ;
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| 10 | ; JMP_DELAY
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| 11 | ; Parameters
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| 12 | ; Nothing
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| 13 | ; Returns:
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| 14 | ; Nothing
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| 15 | ; Corrupts registers:
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| 16 | ; Nothing
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| 17 | ;--------------------------------------------------------------------
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| 18 | %macro JMP_DELAY 0
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| 19 | jmp SHORT %%NextInstruction
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| 20 | %%NextInstruction:
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| 21 | %endmacro
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| 22 |
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| 23 |
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| 24 | ;--------------------------------------------------------------------
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| 25 | ; Mimimun delays (without fetching) with some CPU architectures:
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| 26 | ; 8088/8086: 17 cycles for jump + 5 cycles for last comparison
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| 27 | ; 286: 10 cycles for jump + 4 cycles for last comparison
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| 28 | ; 386: 13 cycles for jump + ? cycles for last comparison
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| 29 | ; 486: 7 cycles for jump + 6 cycles for last comparison
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| 30 | ;
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| 31 | ; LOOP instruction uses two bytes so aligned fetching will require:
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| 32 | ; 8088: 8 cycles (two BYTE reads)
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| 33 | ; 8086: 4 cycles (one WORD read)
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| 34 | ; 286: 2 cycles + wait states (usually 1)
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| 35 | ; 386: ?
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| 36 | ; 486: Fetched only once to internal cache
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| 37 | ;
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| 38 | ; DELAY_WITH_LOOP_INSTRUCTION_NA ; No JUMP_ALIGN
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| 39 | ; DELAY_WITH_LOOP_INSTRUCTION
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| 40 | ; Parameters
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| 41 | ; CX: Loop iterations (0 is maximum delay with 65536 iterations)
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| 42 | ; Returns:
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| 43 | ; CX: Zero
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| 44 | ; Corrupts registers:
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| 45 | ; Nothing
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| 46 | ;--------------------------------------------------------------------
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| 47 | %macro DELAY_WITH_LOOP_INSTRUCTION_NA 0
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| 48 | %%StartOfLoop:
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| 49 | loop %%StartOfLoop
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| 50 | %endmacro
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| 51 |
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| 52 | %macro DELAY_WITH_LOOP_INSTRUCTION 0
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| 53 | ALIGN JUMP_ALIGN
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| 54 | %%StartOfLoop:
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| 55 | loop %%StartOfLoop
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| 56 | %endmacro
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| 57 |
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| 58 |
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| 59 | %endif ; DELAY_INC
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