1 | ; Project name : XTIDE Universal BIOS |
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2 | ; Description : QDI Vision QD6500 and QD6580 VLB IDE controller |
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3 | ; specifications. |
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4 | ; |
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5 | ; Specifications can be found at http://www.ryston.cz/petr/vlb/vlbidechips.html |
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6 | ; QD6580 DOS Driver Analysis: http://www.ryston.cz/petr/qd/dos37.html |
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7 | %ifndef VISION_INC |
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8 | %define VISION_INC |
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9 | |
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10 | ; Possible base addresses for QD6500 and QD6580 |
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11 | QD65XX_BASE_PORT EQU 30h |
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12 | QD65XX_ALTERNATIVE_BASE_PORT EQU 0B0h |
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13 | |
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14 | |
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15 | ; Vision Register offsets from QD chip base port |
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16 | QD6500_IDE_TIMING_REGISTER EQU 0 |
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17 | QD6580_PRIMARY_IDE_TIMING_REGISTER EQU 0 ; QD6500 has only one channel |
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18 | QD65XX_CONFIG_REGISTER_in EQU 1 |
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19 | QD6580_SECONDARY_IDE_TIMING_REGISTER EQU 2 ; Same definitions as Primary IDE Timing Register |
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20 | QD6580_CONTROL_REGISTER EQU 3 |
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21 | |
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22 | |
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23 | ; Bit definitions for QD65xx IDE Timing Register(s) |
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24 | MASK_QD6500IDE_ACTIVE_TIME EQU 7h ; Active time in VLB clocks (bits 0...2) |
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25 | ; 000b = 8 clocks (<= 33 MHz), 9 clocks (>33 MHz) |
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26 | ; 111b = 1 clock (<= 33 MHz), 2 clocks (>33 MHz) |
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27 | MASK_QD6580IDE_ACTIVE_TIME EQU 0Fh ; Active time in VLB clocks (bits 0...3) |
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28 | ; 0000b = 17 clocks, 1111b = 2 clocks |
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29 | |
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30 | MASK_QD6500IDE_RECOVERY_TIME EQU 0F0h ; Recovery time in VLB clocks (bits 4...7) |
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31 | ; 0000b = 18 clocks (<= 33 MHz), 15 clocks (>33 MHz) |
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32 | ; 1111b = 3 clocks (<= 33 MHz), 0 clocks (>33 MHz) |
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33 | MASK_QD6580IDE_RECOVERY_TIME EQU MASK_QD6500IDE_RECOVERY_TIME |
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34 | ; 0000b = 15 clocks, 1101b = 2 clocks |
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35 | POSITON_QD65XXIDE_RECOVERY_TIME EQU 4 |
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36 | |
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37 | |
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38 | ; Bit definitions for QD65xx Config Register (read only) |
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39 | FLG_QDCONFIG_PRIMARY_IDE EQU (1<<0) ; IDE Controller Base Address |
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40 | ; 0 = 170h, 1 = 1F0h |
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41 | FLG_QDCONFIG_ALTERNATIVE_BASE EQU (1<<1) ; QD Vision Controller Base Address |
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42 | ; 0 = 30h, 1 = B0h |
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43 | FLG_QDCONFIG_ID3 EQU (1<<2) ; VLB bus speed |
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44 | ; 0 = > 33 MHz, 1 = <= 33 MHz |
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45 | FLG_QDCONFIG_QD6500STATUS EQU (1<<3) ; QD6500 Enabled/Disabled status |
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46 | ; 0 = Enabled, 1 = Disabled |
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47 | MASK_QDCONFIG_CONTROLLER_ID EQU 0F0h ; QDI Vision Controller Identification nibble |
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48 | |
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49 | ; QDI Vision Controller Identification nibbles |
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50 | ID_QD6500 EQU 1100b |
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51 | ID_QD6580 EQU 1010b |
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52 | ID_QD6580_ALTERNATE EQU 0101b |
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53 | |
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54 | |
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55 | ; Bit definitions for QD6580 Control Register |
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56 | FLG_QDCONTROL_SECONDARY_DISABLED_in EQU (1<<0) ; 0 = Primary and Secondary IDE enabled (Primary at 1F0h and Secondary at 170h) |
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57 | ; 1 = Only Primary IDE enabled (always at 1F0h) |
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58 | FLG_QDCONTROL_HDONLY_in EQU (1<<1) ; 0 = Hard drive or ATAPI device |
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59 | ; 1 = Hard drives only |
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60 | FLG_QDCONTROL_NONATAPI EQU (1<<7) ; Set to 1 for non-ATAPI devices (hard drives, |
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61 | ; probably Read ahead and/or post-write control?) |
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62 | MASK_QDCONTROL_FLAGS_TO_SET EQU 01011111b ; Bits that must be set when writing the Control Register |
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63 | |
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64 | |
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65 | |
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66 | ; Minimum and Maximum Active and Recovery Time Values |
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67 | QD6500_MAX_ACTIVE_TIME_CLOCKS EQU 8 ; VLB clocks |
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68 | QD6500_MIN_ACTIVE_TIME_CLOCKS EQU 1 ; VLB clocks |
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69 | QD6580_MAX_ACTIVE_TIME_CLOCKS EQU 17 ; VLB clocks |
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70 | QD6580_MIN_ACTIVE_TIME_CLOCKS EQU 2 ; VLB clocks |
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71 | QD65xx_MAX_RECOVERY_TIME_CLOCKS EQU 15 ; VLB clocks |
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72 | QD65xx_MIN_RECOVERY_TIME_CLOCKS EQU 2 ; VLB clocks |
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73 | |
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74 | |
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75 | ; Cycle times for different VLB bus clocks |
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76 | VLB_33MHZ_CYCLE_TIME EQU 30 ; ns |
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77 | VLB_40MHZ_CYCLE_TIME EQU 25 ; ns |
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78 | |
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79 | |
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80 | %endif ; VISION_INC |
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